Technological advances in semiconductor integrated circuit (IC) materials, design, processing, and manufacturing have enabled ever-shrinking IC devices, where each generation has smaller and more complex circuits than the previous generation.
As semiconductor circuits composed of devices such as metal-oxide-semiconductor field effect transistors (MOSFETs) are adapted for high voltage applications, such as high voltage lateral diffusion metal-oxide-semiconductor devices (HV LDMOSs) including high voltage insulated gate bipolar transistors (HV IGBTs), problems arise with respect to decreasing voltage performance as the scaling continues with advanced technologies. To prevent punch-through between source and drain, or to reduce resistance of source and drain, standard MOS fabrication process flows may be accompanied by multiple implantations of high concentrations. Substantial substrate leakage and voltage breakdown often occur with device reliability degradation.
Performance of a HV MOS transistor is often limited by its substrate leakage and breakdown voltage (BV) threshold. Substantial substrate leakage reduces switching speed and increases likelihood of unwanted parasitic bipolar junction (BJT) turn-on and latch-up. While various methods including use of full or partial silicon-on-insulator (SOI) substrates has been developed to reduce substrate leakage, a HV LDMOS device having a low substrate leakage and a high breakdown voltage threshold and a method for making the same in a cost effective manner continues to be sought.
Various embodiments of the present invention will be explained in detail with reference to the accompanying drawings.